To reduce the design requirements of application specific integrated circuits (ASIC), libraries of complex components (e.g., "macros") have been developed. These macros can include microprocessors, digital signal processors, bus translators, analog and digital translations, and the like.
Because of the complexity of many macros, different operational features may be required by different users. In a soft macro (one which is synthesized from a high-level description to gate-level), such operational features can be selected by enabling different flags or switches in the high-level description. Unfortunately, soft macros cannot be automatically synthesized, and cannot meet the timing requirements necessary for many high speed applications. For example, although a user may be able to synthesize a processor from a high level description, the resultant processor speed may be inadequate.
The typical solution to the speed deficiencies associated with soft macros is to layout, wire, and fix the physical design of the macro, thereby producing a "hard macro." However, with a hard macro, the macro's features are fixed and, in order to satisfy a wide variety of customer design requirements, many hard macros of the same function must be designed with slightly different features. Clearly, this is an inefficient design method which is not much better than a fully custom design.
The prior art method of providing a plurality of hard macros in a library is generally adequate as long as the complexity of the macros is low enough to preclude the need for customer specific design changes. Correspondingly, the use of soft macros is generally adequate as long as the final circuit speed is not an issue.